The present invention relates to a semiconductor integrated circuit device, and, more particularly, to a memory controller installed in the semiconductor integrated circuit device for controlling memory data read and write.
FIG. 1 is a schematic block diagram of a conventional system LSI (large scale integrated circuit) 100. The system LSI 100 includes a memory 1 such as a DRAM and a semiconductor integrated circuit device (LSI) 2 connected to the memory 1. The LSI 2 includes a CPU 3, a function macro or an internal circuit 4 accessing the memory 1, such as a peripheral circuit, and a control circuit or a memory controller 5 controlling the access of the function macro 4. The memory 1 provides and receives a predetermined signal via internal wiring and external wiring of the LSI 2.
The function macro 4 provides a read/write signal W/R determining an access method, an access request signal REQ, write data WDATA 7:0 (7:0 indicate 7 to 0), and address signals A 22:0 to the memory controller 5. The memory controller 5 provides read data RDATA 7:0 and an acknowledge signal ACK indicating output timing of the read data (input timing of the function macro) to the function macro 4.
FIG. 2 is a schematic block diagram of the memory controller 5 of FIG. 1. The memory controller 5 includes a control circuit 11, an output buffer 12, an input buffer 13, and a flip-flop 14.
The control circuit 11 controls the output buffer 12, which is a three-state buffer, in accordance with the read/write signal W/R so that output data and input data do not conflict. The control circuit 11 provides an internal clock signal ICLK generated using a clock signal CLK—CON to the flip-flop 14. The flip-flop 14 latches the input data provided from the input buffer 13 in response to the internal clock signal ICLK and provides the latched input data or the read data RDATA 7:0 to the function macro 4. Further, the control circuit 11 provides the acknowledge signal ACK to the function macro 4.
FIG. 3 is a timing diagram in the case where data is read from the memory 1 in which CAS latency (CL) is 2. In FIG. 3, various signals transferred between the memory 1 and the memory controller 5 are described using codes of terminals to which corresponding signals are provided. Therefore, changes of the various signals are represented according to a change of a signal in each terminal.
When the request signal REQ is provided to the memory controller 5 at timing (−1), the memory controller 5 issues a first read command (RD1) at the T1 cycle in response to the rising edge of the clock signal CLK—CON. The memory 1 receives a clock signal CLK—DR and a read command RD1 and outputs data (D1) (a data signal D—DR) at a read address BA1 being a time tAC late from the rising edge of the clock signal CLK—DR in response to the read command RD1. The time tAC is necessary for a data output operation of the memory 1. The memory controller 5 receives the data D1 (a data signal D—CON) read from the memory 1 at the T3 cycle.
The internal wiring of the LSI 2 and the external wiring between the LSI 2 and the memory 1 generate a first delay time tD1 when a signal is supplied from the memory controller 5 to the memory 1 and generate a second delay time tD2 when a signal is supplied from the memory 1 to the memory controller 5.
When the cycle of the clock signal CLK—CON is sufficiently long compared with the first and second delay times tD1 and tD2, the memory controller 5 can acquire the data signal D—CON (data D1) at the T3 cycle. Therefore, the memory controller 5 asserts the acknowledge signal ACK matching the acquisition at the T3 cycle. When the acknowledge signal ACK is asserted, the function macro 4 acquires the data D1 in response to the rising edge of the internal clock signal ICLK.
The CPU 3 provides a mode switching signal MODE to the function macro 4 and the memory controller 5 based on the operating state of the LSI 2. The function macro 4 and the memory controller 5 decrease an operation clock frequency in accordance with the mode switching signal MODE. This operation reduces the power consumption of the LSI 2.
The first and second delay times tD1, tD2 depend on the layouts and connection wiring of the LSI 2 and the memory 1. Therefore, when the frequencies of the clock signals CLK—CON, CLK—DR, ICLK increase due to the fast operation speed of the LSI 2, as shown in FIG. 4, the memory controller 5 can acquire the data D—CON only at the T4 cycle or later. The control circuit 11 needs to assert the acknowledge signal ACK at the T4 cycle that is delayed to the extent of one clock cycle.
The first and second delay times tD1, tD2 fluctuate due to a temperature change of operating environment and manufacturing dispersion. When the delay times tD1, tD2 are relatively prolonged or the frequency of the clock signal CLK—CON increases, as shown in FIG. 5, a changing point of the data D—CON and a changing point of the internal clock signal ICLK of the memory controller may close each other. In this case, the setup time of the data D—CON is not sufficiently secured when the internal clock signal ICLK rises, and the function macro 4 cannot stably acquire data.
When the wiring delay times tD1, tD2 are further prolonged or the frequency of the clock signal CLK—CON further increases, as shown in FIG. 6, the memory controller 5 can acquire data at the T5 cycle or later. As shown in FIG. 4, however, when the acknowledge signal ACK is asserted at the T4 cycle, the function macro 4 cannot acquire the data D1. Therefore, assert timing of the acknowledge signal ACK needs to be changed so that data can stably be acquired.
The acquiring point of data (assert timing of the ACK signal) against a fluctuation of the wiring delay time and the application of a clock signal to a high frequency is changed by setting a register or controlling switches of the memory controller 5 by the CPU 3.
The output timing of the data (D—CON) from the memory controller 5, however, dynamically or irregularly changes due to the temperature change of operating environment and manufacturing dispersion. Further, the wiring delay times tD1, tD2 fluctuate and the CLK—CON frequency changes for the purpose of power saving. Therefore, it is difficult to always set an optimum data acquiring point of the function macro 4 (assert timing of the ACK signal) in accordance with these changes.